1. Field of the Invention
This invention relates generally to an apparatus for measuring electrical properties of a semiconductor wafer.
2. Description of Related Art
The determination of electrical properties of a dielectric on a semiconductor wafer and/or a carrier density profile within the semiconductor wafer is a critical factor in the production of these wafers. In order to determine the electrical properties of the wafer, various techniques may be employed, including a capacitance-voltage (CV) measurement technique, a current-voltage (IV) measurement technique, a conductance-voltage (GV) technique and/or current-time (Ct) or lifetime measurement technique.
In some instances, the dopant concentration in the near surface region of a semiconductor surface must be profiled. Typically, in the absence of a metal oxide semiconductor (MOS) layer, this is accomplished using CV measurements, as applied to a Schottky barrier. A Schottky barrier is formed by applying a metal directly to the silicon or semiconductor material surface. However, the Schottky barrier formation process is tedious and time consuming. Further, CV measurements utilizing a Schottky barrier have five Debye length limitation (i.e., the dopant concentration can be profiled to within five Debye length from the surface). Alternatively, an oxide can be grown on the semiconductor material surface, and either a temporary or permanent metal contact can be made to the oxide surface to form a MOS junction. Utilizing a MOS junction yields superior performance, in that the doping concentration can be measured to within one Debye length from the oxide/material interface. However, in some cases, the user does not grow an oxide and, therefore, the Schottky method must be used.
Another problem with current measurement techniques stems from the electrical communication or interference between the object area or test site of the wafer and/or the probe with the surrounding region. The reduction of minority carrier generation from the surrounding region is required. Presently, this communication or interference is minimized by depositing a permanent guard ring 2 onto the oxide or dielectric surface surrounding a deposited test dot or object area 1. (See FIG. 1). However, the use of these deposited guard rings drastically increases processing times.
In order to map the semiconductor material surface, lateral movement between the probe and the wafer during CV and lifetime measurements is required. This lateral movement reduces mapping speeds. Still further, as discussed above, the measurements are subject to error due to interference from minority carriers.
It is, therefore, an object of the present invention to avoid or overcome the above problems and others by providing an apparatus for measuring the electrical properties of a semiconductor wafer having an improved probe configuration which minimizes interference or electrical communication from areas outside of the object area to the object area or the probe. It is another object of the present invention to provide a measurement apparatus that reduces mapping and measurement processing times and costs. Still further objects of the present invention will become apparent to those of ordinary skill in the art upon reading and understanding the following description.
Accordingly, we have invented an apparatus for measuring at least one electrical property of a semiconductor wafer. The apparatus comprises a probe including a shaft having at a distal end thereof a conductive tip. The conductive tip electrically communicates with an object area of the semiconductor wafer. The apparatus includes a means for applying an electrical stimulus between the conductive tip and the object area, as well as a means for measuring a response of the semiconductor wafer to the electrical stimulus and for determining from the response the at least one electrical property of the object area of the semiconductor wafer. The apparatus also includes a probe guard, which surrounds at least the shaft of the probe adjacent the distal end of the probe and which avoids electrical communication between the probe and areas outside of the object area of the semiconductor wafer or insulates the conductive tip from the semiconductor wafer.
In one embodiment, the probe guard completely surrounds the conductive tip of the probe and at least a portion of the shaft. Further, the probe guard is formed from an insulator material.
In another embodiment, the probe guard includes an insulator surrounding the shaft of the probe adjacent the distal end of the probe. In this embodiment, the probe guard also has a conductor surrounding the insulator. Also, it is envisioned that an alternating current voltage bias, a direct current voltage bias and an electrical ground or some combination thereof is applied to the conductor.
In a still further embodiment, the probe guard includes a second insulator surrounding the conductor. In this embodiment, the conductive probe tip can be formed from a conductive material, such as indium tin oxide, which is transparent to light, and the probe can include a light source, such as a light emitting diode (LED), which emits light through the transparent material portion of the probe tip toward the object area of the semiconductor wafer. The probe can also include an opaque portion surrounding the LED in order to prevent light emissions through portions of the probe other than the transparent material portion. In this embodiment, signals may be communicated to the object area via the LED and/or the transparent material conductive probe tip. However, regardless of the introduction technique, it is the response of the probe tip from which the measurements are derived.
The present invention, both as to its construction and its method of operation, together with the additional objects and advantages thereof, will best be understood from the following description of specific embodiments when read in connection with the accompanying drawings.